1. Technical Field of the Invention
The present invention relates to synchronous rectifier circuits. More particularly, the invention relates to synchronous rectifier circuits in which a parasitic inductance associated with the synchronous transistor is utilized to yield significant improvements in circuit operation. Synchronous rectifier circuits designed according to the present invention exhibit minimal dead time, shoot through prevention and Cdv/dt immunity, as well as significant switching loss reduction. The principles of the invention are applicable to all types of synchronous rectifier topology, and to implementation using MOSFETs as well as IGBTs and other types of transistors.
2. Relevant Art
With advances in VLSI technology, digital systems now require lower supply voltage and higher current. Low output voltage and high output current DC/DC converter are widely used to power those systems. Synchronous rectifiers are essential technology for these applications because of the greatly reduced conduction loss compared with diode rectifiers, for example.
For purposes of the description herein, it is to be understood that the synchronous transistor is one which replaces or supplements the diode function.
FIGS. 1(a) and 1(b) show two examples of synchronous rectifier circuits. FIG. 1(a) shows a buck converter including a high side power switching MOSFET Q1 and a low side synchronous MOSFET Q2. The common node between Q1 and Q2 feeds a load Ro through a series inductor Lo and a parallel capacitor Co.
FIG. 1(b) shows an isolated half bridge converter in which a pair of power switching MOSFETs Qp1 and Qp2 drive the primary of a transformer 10. A pair of synchronous MOSFETs Q1 and Q2 connected to the high and low sides of a center tapped secondary of transformer 10 and to a common node 12 again feed a load Ro through a series inductor Lo and a parallel capacitor Co.
In both instances, gate drive for the MOSFETs is provided by a pulse width modulated signal, the duty cycle of which is controlled by a feedback loop (not shown) to provide the desired output current and voltage.
For convenience, the invention will be described mainly in the context of the buck converter topology using MOSFETs, but it has been found that the benefits of the invention are directly applicable to other synchronous rectifier topologies as well, and to circuits using other types of transistors.
In a circuit employing MOSFETs, the parasitic inductance of interest is the common source inductance shared by the drain-source current path and gate driver loop as shown in FIG. 2. The common source inductance LCSI carries the drain source current and the gate charging current. Any voltage induced on LCSI contributes to the VGS of the MOSFET. Because of the importance of VGS on the switching performance of a power MOSFET, common source inductance has very significant impact on the system performance. This is well known to those skilled in the art, and according to conventional practice, great care is taken in circuit layout to reduce common source inductance to as low a value as possible for both the switching and synchronous transistors in synchronous rectifier circuits.
More particularly, because the drain source current of a power MOSFET flows through LCSI, and LCSIis also in the gate driver loop, a change of the drain source current induces a voltage across common source inductance LCSI. This voltage actively modifies the gate source voltage of a power MOSFET. The effect is particularly significant during turn on and turn off when IDS and VGS make fast transitions.
FIG. 3(a) shows the effect of common source inductance during turn on for a power MOSFET Q1 used as an active switch on the high side. When voltage is applied to turn on Q1, the voltage induced on LCSI due to the rising current acts against VGS. This slows down the turn on of the MOSFET. The same effect in the opposite direction can be observed during turn off of Q1 in FIG. 3(b). Simulation studies of a conventionally designed synchronous buck converter circuit having a 12V input and providing a 30 A output at 1.3V with a gate drive switching frequency of 500 kHz (a typical application), indicate that the presence of common source inductance of even 1 nH can result in a power loss of about 6 W.